Hitherto, a computer is caused to execute a test program to perform an operation check test for checking an operation in order to exam the validity of a logic design of the computer or examine an operation of a manufactured computer. There have been known operation check tests such as a high load test for checking whether a computer can normally operate with a load state or not and a conflict test for checking whether a computer can normally operate when a conflict occurs in pipeline processing or not.
For the high load test, an instruction array for test may be required to generate for causing a computer to have a high load state. For the conflict test on the other hand, an instruction array for test may be required to generate for causing a computer to have a conflict state. For example, a scoreboard with which whether registers are in use or not is registered may be used to select a register to be used in instructions and thus generate an instruction array for obtaining a conflict state.
A test instruction array may be a random instruction array for which values of operands of instructions and/or registers designated as operands are generated at random.
However, when an “interruption” occurs while a computer is executing an instruction array for a high load test or conflict test, the computer exits from the test operation until exception processing performed for the interruption ends. This prevents generation of the originally intended high load state or conflict state. The interruption causing a computer to perform exception processing in this way is called an exception interruption.
The exception interruption may occur in a fixed point division in which a division is performed with a divisor “0”, for example. This may require error processing, and the computer therefore terminates the subsequent instructions and performs exception processing of executing a subroutine for error processing. Exception interruption may also occur in a floating point arithmetic with overflow. The occurrence of such overflow causes a computer to stop the subsequent instructions and executes exception processing of performing a subroutine for processing the overflowing value. In this way, when an exception interruption occurs during a high load test or conflict test and the computer is caused to shift to a subroutine for the exception processing, the computer is prevented from acquiring the originally intended high load state or conflict state until the subroutine for exception processing ends.
The prior art has been known which suppresses the occurrence of an exception interruption in testing a computer by using a test instruction array. For example, there has been known a technology which acquires a test instruction array with fewer exception interruptions by changing the conditions such as operand data and/or arithmetic data, for example, for an instruction in which an exception interruption may possibly occur when a computer generates a test instruction array. For the instruction in which an exception interruption has occurred when a computer executed a test instruction array, a technology has been known which stores the parameter causing the exception interruption and excludes the cause parameter from the next test instruction array. Reference may be made to Japanese Laid-open Patent Publication No. 2-244338, Japanese Laid-open Patent Publication No. 6-324904, and Japanese Laid-open Patent Publication No. 2001-222442.
A computer writes the execution result of an instruction with a designated register number to a designated register as an output destination. Thus, when the computer executes the test instruction array, the value that the register holds changes as the processing advances. Therefore, from a test instruction array with a random register number designated as an operand, the value stored in the register is not available in advance when the instruction is executed.
Because the values of the registers are not available in advance when the instruction is executed, an exception interruption may possibly occur with some combinations of values held by the registers when the instruction is executed. For example, when a computer executes a division instruction in which a division is performed by using the value of a register as a divisor, and if the preceding instruction has written “0” to the register, a division instruction with the divisor 0 is performed as a result, thus causing an exception interruption. Similarly, when a computer executes a floating point arithmetic by using the value of a register as an input, the arithmetic result may overflow with some values written to the register by the preceding instruction, also causing an exception interruption.
In this way, for a test using an instruction with a random register number as an operand, it is difficult to identify the correspondence between the instruction and the execution result in advance and set a combination of an instruction and an execution result which may not cause an exception interruption. For that, some combinations of instructions and execution results may possibly cause an exception interruption, and it has been difficult to eliminate the possibility of causing an exception interruption.
The prior art which changes the condition such as operand data assumes that the data of an operand is identified before a test is started. When a test is performed by using the instruction with a register number as an operand, the possibility of causing an exception interruption may still remain.
In the prior art that excludes the parameter of an instruction in which an exception interruption has occurred from the next test instruction array, a cause parameter may not be excluded from the next test instruction array until an exception interruption occurs with it at least once, and it is difficult to prevent the occurrence of the exception interruption. In addition, as the number of stored parameters increases, the frequency of occurrence of exception interruptions can be reduced. However, the occurrence of exception interruptions may not be suppressed unless all parameters which may possibility cause exception interruptions are stored.
In this way, according to the prior arts, the occurrence of exception interruptions may not be eliminated in testing by using an instruction having a random register number as an operand in a test instruction array. A problem also exists that an exception interruption may not be prevented in advance even when the parameters relating to the exception interruptions having occurred in the past are stored.